1. Field of the Invention
The present invention relates to a memory- and logic-embedded semiconductor device in which a memory and a logic devices are formed on a single semiconductor substrate, and also relates to a method of manufacturing the same.
2. Description of the Background Art
FIGS. 39 through 51 are cross-sectional views showing a sequence of process steps in a conventional method of manufacturing a memory- and logic-embedded semiconductor device. Conventional memory and logic-embedded semiconductor devices employ for example, DRAMs with memory cells having CUB (Capacitor Under Bit line) structures for their memory devices and salicided dual gate CMOS transistors for their logic devices.
First, as shown in FIG. 39, by means of the well-known LOCOS isolation or trench isolation technique, and element isolation insulating film 2 is formed in the upper surface of a semiconductor substrate 1 which is, for example, an n-type silicon substrate. Then, p-type well regions 3, 53 and n-type well region 54 are formed in the upper surface of the semiconductor substrate 1. More specifically, the well region 53 is formed in the upper surface of the semiconductor substrate 1 in a region where a memory device is to be formed (hereinafter referred to as a “memory-forming region”), and the well region 54 is formed at the bottom of the well region 53. The well region 3 is formed in the upper surface of the semiconductor substrate 1 in a region where a logic device is to be formed (hereinafter referred to as a “logic-forming region”). Then, channel implantation is performed.
Then, a plurality of gate structures 61 are formed with a predetermined distance from each other on the semiconductor substrate 1 in the memory-forming region. Each of the gate structures 61 is configured such that a gate insulating film 55 using for example silicon oxide film, a gate electrode 56 using for example polycrystalline silicon film, and a silicon oxide film 57 using for example TEOS film are stacked in this order. On the semiconductor substrate 1 in the logic-forming region, a plurality of gate structures 11 are formed with a predetermined distance from each other. Each of the gate structures 11 is configured such that a gate insulating film 5 using for example silicon oxide film, a gate electrode 6 using for example polycrystalline silicon film, and a silicon oxide film 7 using for example TEOS film are stacked in this order.
Using the gate structures 11, 61 and the element isolation insulating film 2 as masks, impurities such as phosphorus or arsenic are ion implanted in relatively low concentrations into the upper surface of the semiconductor substrate 1. This forms n− impurity regions 58a in the upper surface of the semiconductor substrate 1 in the memory-forming region and n− impurity regions 8a in the upper surface of the semiconductor substrate 1 in the logic-forming region.
Then, as shown in FIG. 40, after formation of a silicon nitride film over the entire surface by, for example, CVD, the silicon nitride film is etched by anisotropic dry etching techniques which exhibit a high etch rate in a direction along the depth of the semiconductor substrate 1. This forms sidewalls 60 on the side surfaces of the gate structures 61 and sidewalls 10 on the side surfaces of the gate structures 11.
Then, using the gate structures 11 and 61, the element isolation insulating film 2 and the sidewalls 10 and 60 as masks, impurities such as phosphorus or arsenic are ion implanted in relatively high concentrations into the upper surface of the semiconductor substrate 1. This forms n+ impurity regions 58b in the upper surface of the semiconductor substrate 1 in the memory-forming region and n+ impurity regions 8b in the upper surface of the semiconductor substrate 1 in the logic-forming region.
Through the above process steps, a plurality of source/drain regions 59, each consisting of the impurity regions 58a and 58b, are formed with a predetermined distance from each other in the upper surface of the semiconductor substrate 1 in the memory-forming region, and the gate structures 61 each are formed on the upper surface of the semiconductor substrate 1 between the adjacent source/drain regions 59. Also, a plurality of source/drain regions 9, each consisting of the impurity regions 8a and 8b, are formed with a predetermined distance from each other in the upper surface of the semiconductor substrate 1 in the logic-forming region, and the gate structures 11 each are formed on the upper surface of the semiconductor substrate 1 between the adjacent source/drain regions 9.
For the following reason, the impurity regions 8b and 58b are formed deeper than the impurity regions 8a and 58a. That is, during formation of a cobalt silicide film 12 later to be described on the semiconductor substrate 1, the cobalt silicide film 12 may be partly formed deeply. Thus, in order to avoid electrical connections between the cobalt silicide film 12 and the well regions 3 and 53, the impurity regions 8b and 58b are formed deeper than the impurity regions 8a and 58a. At this time, if the concentration of the impurity regions 58b is too high, a leakage current flowing in a direction along the channel may be increased, thereby causing deterioration in charge retention properties (also referred to as “refresh properties”) of the memory device. To prevent such degradation, the concentration of the impurity regions 58b in the memory-forming region is set to be lower than that of the impurity regions 8b in the logic-forming region.
Then, as shown in FIG. 41, the silicon oxide films 57 of the gate structures 61 and the silicon oxide films 7 of the gate structures 11 are removed with, for example, hydrofluoric acid.
Then, a cobalt film is formed over the entire surface using, for example, a sputtering method. Then, for example by thermal treatment using a lamp annealer, cobalt is reacted with contacting silicon. Thereby, as shown in FIG. 42, the upper surface of the semiconductor substrate 1 is partially silicided to form the cobalt silicide films 12 on the source/drain regions 9 and 59. Simultaneously, the upper surfaces of the gate electrodes 6 and 56 are silicided to form the cobalt silicide films 12. This results in the formation of the gate structures 11 each having the cobalt silicide film 12 on its gate electrode 6 and the formation of the gate structures 61 each having the cobalt silicide film 12 on its gate electrode 56. Afterwards, the unreacted cobalt film is removed.
Then, as shown in FIG. 43, an insulating layer 19 consisting of a stopper film 13 and an interlayer insulation film 14 is formed on the semiconductor substrate 1 to cover the gate structures 11 and 61. More specifically, the stopper film 13 is formed over the entire surface and thereafter the interlayer insulation film 14 is formed on the stopper film 13. The interlayer insulation film 14 is then planarized by, for example, CMP. This forms the insulating layer 19 having a flat upper surface on the semiconductor substrate 1. Here, the stopper film 13 is formed of, for example, silicon nitride film and the interlayer insulation film 14 is formed of, for example, BPTEOS film.
Then, as shown in FIG. 44, contact plugs 16 and 66 are formed in the insulating layer 19. The contact plugs 16 are electrically connected through the cobalt silicide films 12 to the semiconductor substrate 1 in the logic-forming region, and their upper surfaces are exposed from the interlayer insulation film 14 of the insulating layer 19. The contact plugs 66 are electrically connected through the cobalt silicide films 12 to the semiconductor substrate 1 in the memory-forming region, and their upper surfaces are exposed from the interlayer insulation film 14 of the insulating layer 19. Hereinbelow, concrete expression is given to a method of forming the contact plugs 16 and 66.
First, contact holes 65 which extend to the cobalt silicide films 12 on the semiconductor substrate 1 in the memory-forming region and contact holes 15 which extend to the cobalt silicide films 12 on the semiconductor substrate 1 in the logic-forming region are formed in the insulating layer 19.
To form the contact holes 15 and 65, a photoresist (not shown) having a predetermined opening pattern is first formed using photolithographic techniques on the interlayer insulation film 14 of the insulating layer 19. Then, using the photoresist as a mask and the stopper film 13 as an etch stop, the interlayer insulation film 14 is removed by etching. The etching at this time adopts anisotropic dry etching using a gas mixture of C5F8, O2 and Ar. The photoresist is then removed and the exposed stopper film 13 is also removed by etching. The etching at this time adopts anisotropic dry etching using a gas mixture of CHF3, O2 and Ar. Thereby, the contact holes 15 which are located on the sides of the gate electrodes 6 above the source/drain regions 9 and the contact holes 65 which are located on the sides of the gate electrodes 56 above the source/drain regions 59 are formed in the insulating layer 19 in the logic-forming region and the memory-forming region, respectively.
Then, a multilayer film consisting of a barrier metal layer formed of, for example, titanium nitride and a high-melting metal layer formed of, for example, titanium or tungsten are formed over the entire surface. Then, the multilayer film on the upper surface of the insulating layer 19 is removed by CMP. This forms the contact plugs 16 which are formed of the barrier metal layer and the high-melting metal layers and fill in the contact holes 15, and the contact plugs 66 which are formed of the barrier metal layer and the high-melting metal layers and fill in the contact holes 65. Consequently, the source/drain regions 59 and the contact plugs 66 are electrically connected to each other, and the source/drain regions 9 and the contact plugs 16 are electrically connected to each other. Although not shown, contact plugs which are electrically connected through the cobalt silicide films 12 to the gate electrodes 56 or 6 are also formed in the insulating layer 19.
Then, as shown in FIG. 45, an insulating layer 20 consisting of a stopper film 17 and an interlayer insulation film 18 is formed over the entire surface. More specifically, the stopper film 17 formed of, for example, silicon nitride film is first formed over the entire surface. Then, the interlayer insulation film 18 is formed on the stopper film 17. This forms the insulating layer 20 on the insulating layer 19 and the contact plugs 16 and 66. The interlayer insulation film 18 is formed of, for example, BPTEOS film.
Then, as shown in FIG. 46, openings 69 are formed in the insulating layer 20 to expose some of the plurality of contact plugs 66, more specifically, the contact plugs 66 which are each electrically connected to one of the adjacent source/drain regions 59.
To form the openings 69, a photoresist (not shown) having a predetermined opening pattern is first formed on the interlayer insulation film 18 of the insulating layer 20. Then, using the photoresist as a mask and the stopper film 17 as an etch stop, the interlayer insulation film 18 is removed by etching. The etching at this time adopts anisotropic dry etching using a gas mixture of C5F8, O2 and Ar. The photoresist is then removed and the exposed stopper film 17 is also removed by etching. The etching at this time adopts anisotropic dry etching using a gas mixture of CHF3, O2 and Ar. This forms the openings 69 in the insulating layer 20.
Then, DRAM memory cell capacitors which are in contact with the exposed contact plugs 66 are formed in the openings 69. More specifically, a metal film including a high-melting metal such as ruthenium is formed over the entire surface. The openings 69 are then covered with a photoresist (not shown) and the metal film on the upper surface of the interlayer insulation film 18 is removed by anisotropic dry etching. This forms, as shown in FIG. 47, lower electrodes 70 of the capacitors including a high-melting metal such as ruthenium, in the openings 69. Although the metal film on the upper surface of the interlayer insulation film 18 is removed by anisotropic dry etching, it may be removed by CMP.
Then, after an insulation film of tantalum pentoxide and a metal film including a high-melting metal such as ruthenium are stacked in this order over the entire surface, those films are patterned using a photoresist. This forms, as shown in FIG. 48, dielectric films 71 of the capacitors, which are formed of tantalum pentoxide, and upper electrodes 72 of the capacitors, which include a high-melting metal such as ruthenium, thereby completing the formation of the capacitors 82 in the openings 69.
Then, as shown in FIG. 49, an insulating layer 23 is formed over the entire surface and planarized by CMP. That is, the insulating layer 23 is formed on the interlayer insulation film 18 of the insulating layer 20 to cover the capacitors 82. The insulating layer 23 is formed of, for example, TEOS film and serves as an interlayer insulation film.
Then, contact holes 24 and 74 are formed in the insulating layers 20 and 23. The contact holes 24 extend from the upper surface of the insulating layer 23 to the contact plugs 16, and the contact holes 74 extend from the upper surface of the insulating layer 23 to the contact plugs 66 which are not in contact with the capacitors 82.
To form the contact holes 24 and 74, a photoresist (not shown) having a predetermined opening pattern is first formed on the insulating layer 23. Then, using the photoresist as a mask and the stopper film 17 as an etch stop, the insulating layer 23 and the interlayer insulation film 18 are removed by etching. The etching at this time adopts anisotropic dry etching using a gas mixture of C5F8, O2 and Ar. The photoresist is then removed and the exposed stopper film 17 is also removed by etching. The etching at this time adopts anisotropic dry etching using a gas mixture of CHF3, O2 and Ar. This forms the contact holes 24 and 74. Although not shown, contact holes which extend from the upper surface of the insulating layer 23 to the upper electrodes 72 are also formed in the insulating layers 23, simultaneously with the contact holes 24 and 74.
Then, as shown in FIG. 50, contact plugs 25 of barrier metal layer and high-melting metal layer are formed to fill in the contact holes 24, and contact plugs 75 of barrier metal layer and high-melting metal layer are formed to fill in the contact holes 74. More specifically, a multilayer film formed of a barrier metal layer of, for example, titanium nitride, and a high-melting metal layer of, for example, titanium or tungsten is formed over the entire surface, with the barrier metal layer under the high-melting metal layer. Then, the multilayer film on the upper surface of the insulating layer 23 is removed by CMP. This forms the contact plugs 25 which are electrically connected to the contact plugs 16 and whose upper surfaces are exposed from the insulating layer 23, and the contact plugs 75 which are electrically connected to the contact plugs 66 not in contact with the capacitors 82 and whose upper surfaces are exposed from the insulating layer 23.
Then, as shown in FIG. 51, aluminum interconnections 127 sandwiched from above and below between titanium nitride layers 126 and 128 are formed on the insulating layer 23 to be electrically connected to the contact plugs 25, and aluminum interconnections 177 sandwiched from above and below between titanium nitride layers 176 and 178 are formed on the insulating layer 23 to be electrically connected to the contact plugs 75. The aluminum interconnections 177 are bit lines of the DRAM memory cells.
Through the aforementioned process steps, a memory device is formed in the memory-forming region and a logic device is formed in the logic-forming region.
The aforementioned conventional technique is disclosed in the inventors' early Japanese patent application No. 2002-090483.
Prior art reference information as to semiconductor devices with DRAM memory cells includes Japanese laid-open patent applications No. 8-107188, 11-307742 and 2000-307085.
As above described, it has been difficult in the conventional techniques to reduce the interconnect resistance in the semiconductor device since aluminum interconnections are formed in the upper layer. Accordingly, it has been difficult to improve the performance of the memory device formed in the memory-forming region and the logic device formed in the logic-forming region.